1. Field of the Invention
This invention relates to the dense packaging of electronic circuitry, and specifically to the stacking of integrated circuit (IC) chips, or die.
2. Description of the Prior Art
Stackable IC chip layers were disclosed in U.S. Pat. No. 5,953,588 which permit chips having different functions and therefore different areas to be stacked as if they were same size chips, using stacking and electrical connection techniques and tools which have been developed for same size chips. The new units were referred to as xe2x80x9cneoxe2x80x9d (or xe2x80x9cpseudoxe2x80x9d or xe2x80x9cvirtualxe2x80x9d) chips. In addition to the advantage of being able to use chips of varying sizes in a given stack, that technology permits the processing and stacking of chips purchased as individual die, which are more readily available than chips purchased in wafer form. Furthermore, the chips purchased as individual die are generally xe2x80x9cknown goodxe2x80x9d die, which have been xe2x80x9cburned inxe2x80x9d, and are therefore pre-tested prior to stacking.
A re-wafering process is used, in which a neo-wafer is formed encapsulating known good chips, so that the chips can be prepared for stacking by covering their active surfaces with a dielectric layer, forming vias through the dielectric layer to reach the terminals on the respective chips, and metallizing to provide electrical connections from the chip terminals to side surfaces of the layer, which are created when the neo-wafer is diced, or sliced, to provide individual layers ready for stacking.
Prior to this technology the extra steps required preparatory to stacking were sometimes carried out while the chips were still in their original wafer form. The wafer concept is almost universally used to simultaneously form integrated circuits (ICs) in numerous locations in the wafer, so that a multiplicity of separate IC chips will be created when the wafer is diced. Since preparation for stacking requires that the chip surfaces be metalized to connect their terminals to suitable access planes on the stack, manufacturing steps beyond the normal wafer processing steps are required, if stacking is intended. In some cases, chips in TSOP (packaged) form have been electrically connected to external circuitry by means of metal frames which are formed as part of the TSOP structure.
In this process the chips which have been previously formed in a wafering process, and tested to insure their performance, need to be re-wafered, so they can be processed for subsequent stacking. Even in the case of a single chip, it is not feasible to perform the pre-stacking processing steps without using a neo-wafer, which proves a large enough body to permit efficient handling. Of course, the manufacturing process is much more cost effective if the neo-wafer contains a plurality of pre-formed, pre-tested chips which can be simultaneously prepared for stacking. The neo-wafer is subsequently diced to form individual layers ready for stacking. In effect, two wafering and dicing processes are used to facilitate stacking of chip-encapsulating layers.
The primary challenge in using a neo-wafer containing multiple die is the accurate location of each die. With multiple die in the wafer, the accuracy necessary to locate each die prior to potting creates a potential alignment problem.
The re-wafering process was improved in U.S. Pat. No. 6,117,704 by making location of chips (die) in the neo-wafer highly accurate, and by making it more feasible to include multiple chips in the neo-wafer. The neo-wafer is so structured that each chip it contains is precisely located by use of a single masking step to obtain exact location of the known good chips, which are inserted in the neo-wafer and then covered by potting material. Then the chips in the neo-wafer are simultaneously processed to prepare them for stacking. They are stacked after they have been diced from the neo-wafer.
Since, with the present invention, the locations of the chips in the neo-wafer are controlled by photo patterning (photo-lithography), their relative locations are determined with the very high precision inherent in the use of a single mask to control the locations of all chips in the neo-wafer.
Another advantage of the improved process is that any leakage of potting material onto the active (upper) surfaces of the chips in the neo-wafer does not affect the electrical terminals on the chips, so that removal of any such leaked material is not required, and increased reliability of the electrical connection is obtained.
The benefits of the improved prior art are obtained by using a wafer frame, sometimes called a xe2x80x9cpicture framexe2x80x9d, having a plurality of separate chambers, or cavities, into which the individual known good chips are inserted. The chips have conductive bumps which extend into and through pre-formed small holes (vias) in the surface of the wafer frame. The via holes have been formed using photo-lithography with a single mask for the entire neo-wafer, thus insuring precise location of the via holes relative to one another. This insures precise location of the separate chips relative to one another, and provides terminals accessible for electrical connections.
The invention is a method of preparing a pre-formed integrated circuit chip for encapsulation in an electronic package, comprising the steps of forming an interconnect assembly separately from the pre-formed integrated circuit chip; forming a plurality of conductive bumps connected to the terminals of the integrated circuit chip; bonding the interconnect assembly to the prepared integrated circuit chip; and passivating the bonded interconnect assembly and the prepared integrated circuit chip into an integral structure to provide the electronic package.
The step of forming an interconnect assembly comprises forming the interconnect assembly on a releasable substrate.
The step of forming an interconnect assembly comprises forming at least one test pad in an interconnect layer, which at least one test pad can be accessed and electrically connected on opposing sides of the test pad.
The step of forming at least one test pad forms a test pad having gold on opposing sides of the test pad and sandwiched therebetween a conductive field metal.
The step of forming an interconnect assembly comprises forming at least one test pad in a plurality of stacked interconnect layers, each of which at least one test pad in each interconnect layer can be accessed and electrically connected on opposing sides of the test pad.
The step of forming a plurality of conductive bumps connected to the terminals of the integrated circuit chip form a metallic bump making connection to a terminal on the integrated circuit chip and a solder layer disposed on the metallic bump.
The step of forming an interconnect assembly comprises forming at least one test pad in an interconnect layer, which at least one test pad can be accessed and electrically connected on opposing sides of the test pad, and wherein the step of bonding the interconnect assembly to the prepared integrated circuit chip flip bonds the solder layer onto one side of the test pad.
The step of passivating the bonded interconnect assembly and the prepared integrated circuit chip into an integral structure to provide the electronic package comprises underfilling the prepared integrated circuit chip with an insulating material to remove all voids between the prepared integrated circuit chip and the interconnect assembly.
The step of passivating the bonded interconnect assembly and the prepared integrated circuit chip into an integral structure to provide the electronic package comprises potting the interconnect assembly and the prepared integrated circuit chip into an integral package.
The step of passivating the bonded interconnect assembly and the prepared integrated circuit chip into an integral structure to provide the electronic package comprises potting the interconnect assembly and the prepared integrated circuit chip into an integral package.
The method further comprises the step thinning the prepared integrated circuit chip.
The method further comprises the step of accessing the prepared integrated circuit chip through electrical connection to the at least one test pad through a surface thereof opposing the surface of the test pad contacting a terminal of the prepared integrated circuit chip to test the prepared integrated circuit chip.
A plurality of interconnect assembly and prepared integrated circuit chips are bonded together to form a corresponding plurality of electronic packages. In this case the method comprises the step of releasing the plurality of electronic packages from each other. The method further comprises the step of testing the interconnect assembly and bonding a tested interconnect assembly in the step of bonding the interconnect assembly to the prepared integrated circuit chip only if the interconnect assembly tested good. The step of forming the plurality of interconnect assemblies comprises forming the interconnect assemblies simultaneously in a wafer and individually bump bonding the plurality of prepared integrated circuit chips to successfully tested ones of the interconnect assemblies.
The invention further comprises an electronics package having a structure formed by the above method.
While the apparatus and method has or will be described for the sake of grammatical fluidity with functional explanations, it is to be expressly understood that the claims, unless expressly formulated under 35 USC 112, are not to be construed as necessarily limited in any way by the construction of xe2x80x9cmeansxe2x80x9d or xe2x80x9cstepsxe2x80x9d limitations, but are to be accorded the full scope of the meaning and equivalents of the definition provided by the claims under the judicial doctrine of equivalents, and in the case where the claims are expressly formulated under 35 USC 112 are to be accorded full statutory equivalents under 35 USC 112. The invention can be better visualized by turning now to the following drawings wherein like elements are referenced by like numerals.